This invention relates to a single chip microcomputer and, more particularly, to a single chip microcomputer with a built-in EEPROM (Electrically Erasable and Programmable Read Only Memory).
A central processing unit, a data memory, a program memory, a bus system and an interface are integrated on a single semiconductor chip, and is called as xe2x80x9csingle chip microcomputerxe2x80x9d. The program memory is usually implemented by a mask ROM (Read Only Memory), and programmed instructions are stored in the mask ROM during the fabrication of the single chip microcomputer. A semiconductor wafer is divided into narrow areas, and the narrow areas are respectively assigned to individual products of the single chip microcomputer. Deposition steps, patterning steps, doping steps and other well-known steps are repeated for the fabrication of the single chip microcomputer, and the manufacturer obtains semimanufactured products of the single chip microcomputer. The mask ROM is incomplete in the semimanufactured products. An array of filed effect transistors forms the mask ROM, and is formed in the semimanufactured product of the single chip microcomputer. The mask ROM is programmed through a selective channel doping. The field effect transistors are selectively doped with a dopant impurity. Selected field effect transistors are changed to the normally-on type through the doping, and the others remain in the normally-off type. These two kinds of field effect transistors are corresponding to the two logic levels, and store programmed instructions in the mask ROM. Thus, the single chip microcomputer is unity, and the mask ROM is not separable from the other components. Moreover, the programmed instructions are non-rewritable.
The single chip microcomputer has found a wide variety of application. The control of power unit in the automobile is a typical example of the application. The single chip microcomputer forms an essential component part of a controlling unit, and the controlling unit is installed into the automobile. The single chip microcomputer sequentially executes the programmed instructions stored in the program memory, and controls the fuel injection, the revolution of the engine and so forth. A bug is not avoidable from the programmed instructions stored in the mask ROM. After the installation of the control unit into an automobile, the bug may be found. The automobile manufacturer announces the obligation to replace the control unit with a new one to the user. As described hereinbefore, the programmed instructions are non-rewritable, and the mask ROM is not separable from the single chip microcomputer. This means that the automobile manufacturer is to change the control unit with a new one. The replacement is a great expense.
In order to reduce the loss, the semiconductor manufacturer replaces the mask ROM with an EEPROM (Electrically Erasable and Programmable Read Only Memory). The EEPROM includes addressable memory cells, and the addressable memory cell is implemented by a floating gate type field effect transistor. When the manufacturer stores the programmed instructions into the memory cell array, electrons are selectively accumulated in the floating gates of the memory cells, and, accordingly, change the threshold of the selected memory cells. The high threshold and the low threshold are corresponding to the two logic levels, and the programmed instructions are stored in the form of different threshold in the memory cell array of the EEPROM.
The programmed instructions are erasable, new programmed instructions are stored in the memory cell array of the EEPROM. When the accumulated electrons are evacuated from the floating gates of the memory cells, the programmed instructions are erased from the memory cell array. After the erasing, electrons are selectively accumulated in the floating gates of the memory cells, again, and a set of new programmed instructions is stored in the memory cell array of the EEPROM. Although the program memory implemented by the EEPROM is not separable from the single chip microcomputer, the programmed instructions are rewritable. If a bug is found, the automobile manufacturer only rewrites the programmed instructions stored in the EEPROM, and the repairing work is not so expensive. For this reason, the single chip microcomputer with built-in EEPROM is in great demand.
The single chip microcomputer with built-in EEPROM has been improved in data processing capability, and a large program memory and a large data memory are required for complicated jobs. The data bus has been changed from 4 bits through 8 bits and 16 bits to 32 bits. The address lines have been also increased to 12 bits-32 bits, and the data storage capacity of the EEPROM is 1 kilobyte to 100 kilobytes. Thus, a large EEPROM is incorporated in the single chip microcomputer for the programmed instructions.
Upon completion of the fabrication process, the manufacturer checks the products to see whether or not all the components are operable without any trouble. The single chip microcomputer supplies an address signal from the central processing unit to the program memory, and the programmed instruction is supplied from the program memory to the central processing unit. Thus, the address signal and the programmed instruction are internally propagated between the components, and are not taken out from the single chip microcomputer. For this reason, the manufacturer tests the products before separation from the semiconductor wafer into the chips.
It is possible to carry out tests for the central processing unit, the random access memory, the interfaces/input/output ports and the timer within a short time. However, the test on the EEPROM consumes a long time. This is because of the fact that the injection of electron into a floating gate and the evacuation of electron therefrom are time-consuming. The testing system requires several milliseconds for each EEPROM cell, and the total time period for the EEPROM cell array is tens minutes. A semiconductor wafer is shared between products of the single chip microcomputer, and several hours are consumed for the tests on each semiconductor wafer. This results in low productivity. In the following description, the semiconductor chips before the separation of the semiconductor wafer are referred to as xe2x80x9csemiconductor areasxe2x80x9d.
The EEPROM is tested as follows. The first method is a diagnosis by using a built-in test circuit. The test circuit is integrated on the semiconductor area together with the other components during the fabrication process. The test circuit sequentially addresses the EEPROM cells, and writes a test pattern into the EEPROM cells. Thereafter, the test circuit reads out the test pattern, and compares the read-out test pattern with the write-in test pattern to see whether or not the EEPROM cells have maintained the test pattern without inversion of a test bit. When the read-out test pattern is consistent with the write-in test pattern, the test circuit outputs a diagnostic signal representative of the diagnosis.
A built-in test program is used in the second method. The central processing unit sequentially fetches the programmed instructions for the test, and executes the programmed instructions for generating an address signal and a test pattern. The address signal is supplied to the EEPROM cells so as to sequentially select the EEPROM cells from the cell array. The test pattern is written into the selected EEPROM cells. Upon completion of the write-in, the central processing unit sequentially addresses the EEPROM cells, and the test pattern is read out from the EEPROM cells. The read-out test pattern is compared with the write-in test pattern to see whether or not the EEPROM cells have maintained the test pattern without inversion of a test bit. When the read-out test pattern is consistent with the write-in test pattern, the central processing unit diagnoses the EEPROM cells as non-defective.
The third method is a diagnosis by using an external testing system. The testing system is equipped with a probe card, and the probe card has a lot of probes. On the other hand, the single chip microcomputer has additional input/output ports for the test. The testing system advances the probe card toward the semiconductor wafer, and the probes are brought into contact with the input/output ports in a selected semiconductor area. The testing system supplies an address signal and a test pattern through the probes and the input/output port to the address lines and the data bus in the selected semiconductor area, and the test pattern is written into the EEPROM cells. Then, the test pattern is read out from the EEPROM cells through the input/output port to the testing system, and the testing system checks the read-out test pattern to see whether or not the EEPROM cells have maintained the test pattern without inversion of a test bit. When the read-out test pattern is consistent with the write-in test pattern, the testing system diagnoses the EEPROM cells as non-defective.
The first method and the second method are not reliable, because a defective built-in test circuit and a program sequence with a bug make a wrong diagnosis. The third method seldom makes the wrong diagnosis. However, the additional input/output ports are required for the third method. The address code and the instruction code have been increased in width. A built-in EEPROM is addressed with a sixteen-bit address signal, and the instruction code consists of thirty-two bits. The testing system requires the additional input/output ports consisting of a large number of communication pads, and the manufacturer feels the assignment of the large number of pads to the additional input/output ports difficult. This is the first problem inherent in the third testing method.
Another problem is difficulty in parallel test. As described hereinbefore, the test on the single chip microcomputer with the built-in EEPROM is time-consuming, and a parallel test for plural semiconductor areas is desirable. However, there is a limit on the probes. A standard testing system is communicable with only two hundred and fifty-six probes, and the probes are formed in a circular area of ten to fifteen centimeters in diameter. The testing system is expected to concurrently communicate with the input/output ports formed in the adjacent semiconductor areas during the parallel test. The communication pads are laid out on the same pattern in every semiconductor area. The manufacturer needs to supply the same signals to the corresponding communication pads, and complicatedly arranges the probes on the probe card across the boundary between the adjacent semiconductor areas. Thus, the parallel test is less feasible on the semiconductor wafer.
A probe card is proposed in Japanese Patent Publication of Unexamined Application No. 2-189946. The Japanese Patent Publication of Unexamined Application proposes to arrange the communication pads 20 for the test along two edges of a semiconductor chip 22 as shown in FIG. 1 of the drawings. The communication pads 20 for the test are indicated by hatching lines for discrimination from the other pads. A testing system can concurrently communicate with plural semiconductor chips 22 as shown in FIG. 2, because the probes 24 of the probe card are laid out in parallel without any crossing. Although the arrangement of pads and the probe card allow the testing system to carry out the parallel test, the testing system is merely communicable with the semiconductor chips arranged in a single row, and the length of the probe card sets a limit on the number of semiconductor chips to be concurrently tested.
It is therefore an important object of the present invention to provide a single chip microcomputer with a built-in EEPROM, which permits a testing system to concurrently test products more than those of the semiconductor chips tested in the Japanese Patent Publication of Unexamined Application.
The present inventor contemplated the problem, and noticed that a probe card was available for two rows of products if the communication pads of each product were arranged along a single edge of the semiconductor chip 22.
The present inventor was able to arrange the communication pads for the EEPROM test along a single edge in so far as the storage capacity of the EEPROM was relatively small. However, when the storage capacity was increased, it was difficult to arrange the communication pads along a single edge. In detail, a single chip microcomputer had thirteen 8-bit input/output ports, and the built-in EEPROM communicated with the central processing unit through a 32-bit address bus and a 16-bit data bus. A hundred and sixty communication pads were formed along the periphery of the single chip microcomputer, and forty pads were arranged along each edge of the semiconductor chip. This meant that the communication pads for the EEPROM test were limited to forty. The testing system required sixteen data lines, thirty-two address lines, two power supply lines and at least five control signal lines for the EEPROM test. The total number of communication pads to be required was at least fifty-five. Sixty communication pads were preferable for the EEPROM test. The present inventor concluded that a multiple usage of the communication pads resulted in the single row of communication pads for the large EEPROM.
In accordance with one aspect of the present invention, there is provided a single chip microcomputer fabricated on a semiconductor chip, having a data processing mode and a test mode and comprising a central processing unit executing programmed instructions expressing at least one job in the data processing mode, an electrically erasable and programmable read only memory storing pieces of information used in the data processing mode for the central processing unit and tested to see whether the pieces of information are properly maintained in the test mode, plural communication pads classified into a first communication pad group used only for the job in the data processing mode and a second communication pad group available for the test in the test mode and arranged along an edge of the semiconductor chip and plural conductive paths selectively connected between the plural communication pads, the central processing unit and the electrically erasable and programmable read only memory.